Demands for a semiconductor memory device realizing high integration and high capacity have steadily increased. An example of such a semiconductor device is a flash memory, which is mainly used in potable electronic devices. In addition, semiconductor memory devices having a non-volatile material instead of a capacitor, as used in DRAM, have emerged.
For example, such semiconductor devices include a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) layer, and a phase change memory device using chalcogenide alloys. In particular, a resistance variable memory device, such as the phase change memory device, can be manufactured by a relatively simple process and embodied into a high capacity memory at a relatively low cost.
FIG. 1 illustrates a memory cell of a typical resistance variable memory device. Referring to FIG. 1, a memory cell 10 of a resistance variable memory device includes a variable resistor C and an access transistor M.
The variable resistor C is connected to a bit line BL. The access transistor M is connected between the variable resistor C and a ground terminal. A word line WL is connected to a gate of the access transistor M. When a predetermined voltage is applied to the word line WL, the access transistor M is turned on. When the access transistor M is turned on, the variable resistor C receives a current Ic via the bit line BL.
The variable resistor C includes a phase change material (not shown). The phase change material has two stable states, that is, a crystal state or an amorphous state—according to temperature. That is the phase change material is changed into the crystal state or the amorphous state in accordance with a current Ic supplied via the bit line BL. The phase change memory device programs data using the above property of the phase change material.
FIG. 2 is a graph illustrating the property of a phase change material. The reference numeral 1 shows a condition for the phase change material to be changed into an amorphous state, and the reference numeral 2 shows a condition for the phase change material to be changed into a crystal state.
Referring to FIG. 2, a phase change material (such as “GST”) is changed into the amorphous state after being heated above the melting temperature Tm by supplying the current Ic for duration T1. GST is a chalcogenide alloy of germanium, antimony and tellurium (GeSbTe). The amorphous state is usually referred to as a reset state, and data ‘1’ is stored in this state.
In contrast, the phase change material is changed into the crystal state after being heated between a crystallization temperature Tc and the melting temperature Tm for duration T2, which is longer than T1. The crystal state is commonly referred to as a set state, and data ‘0’ is stored in this state. A memory cell has the characteristic that its resistance varies according to an amorphous volume of the phase change material. The resistance of the memory cell is highest at the amorphous state, and lowest at the crystal state.
In recent years, a technology for storing two or more bits of data at one memory cell has been developed. This memory cell is called a multi-level cell (MLC), and has a multi-state according to the resistance distribution. In a resistance variable memory device, the MLC further includes intermediate states between the reset state and the set state. A method for programming a resistance variable memory device having the MLC is disclosed in U.S. Pat. No. 6,625,054 (hereinafter, referred to as ‘054 patent’).
FIGS. 3A through 3D are graphs illustrating a method of programming a resistance variable memory device having a typical MLC, where each of FIGS. 3A-3D represents a different set of programming signals, in accordance with the prior art. The programming method as illustrated in FIGS. 3A-3D is disclosed in the 054 patent. Referring to FIGS. 3A-3D, different times T0-T11 are denoted on the TIME axis and currents I0 (min), I1(max in FIGS. 3A, B, D) and I2 (max in FIG. 3C) are denoted on the CURRENT axis. The memory cell represented in each figure includes four states according to a falling time of a program pulse. A case where the memory cell is in a reset state is called a state “11”, and a case where the memory cell is in a set state is called a state “00”. The memory cell further has a state “10” and a state “01” in accordance with an amorphous volume of a phase change material.
According to the 054 patent, the phase change memory device programs two bits into one memory cell by controlling the falling time of the current pulse applied to the memory cell. The 054 patent uses a characteristic that the amorphous volume of the phase change material decreases as the falling time of the current pulse increases.
There should be no difference between a resistance at several nanoseconds after programming and a resistance at several or several tens of days after programming so that the typical resistance variable memory device, e.g., the resistance variable memory device in the 054 patent, performs a normal MLC operation. However, the resistance of the resistance variable memory device will vary according to a lapse of time due to the property of the phase change material (GST). This phenomenon is called resistance drift, which can negatively affect the reliability of the device. It would be advantageous to devise a resistance variable memory device that minimizes or substantially eliminates resistance drift.